The present invention relates generally to forming layers in integrated circuits, and more particularly to depositing thin films with graded impurity concentrations.
There are numerous semiconductor process steps involved in the development of modem day integrated circuits (ICs). From the initial fabrication of silicon substrates to final packaging and testing, integrated circuit manufacturing involves many fabrication steps, including photolithography, doping, etching and thin film deposition. As a result of these processes, integrated circuits are formed of microscopic devices and wiring amid multiple layers.
A basic building block of the integrated circuit is the thin film transistor (TFT). The transistor includes a gate dielectric layer sandwiched between a xe2x80x9cmetalxe2x80x9d layer and the semiconductor substrate, thus the acronym xe2x80x9cMOSxe2x80x9d for metal-oxide-semiconductor. In reality, the gate electrode is typically formed of conductively doped silicon rather than metal. The gate dielectric most commonly employed is SiO2 or silicon dioxide.
Today""s market demands more powerful and faster integrated circuits. In pursuit of such speed and lower power consumption, device packing densities are continually being increased by scaling down device dimensions. To date, this scaling has reduced gate electrode widths to less than 0.25 xcexcm. Currently, commercial products are available employing gate widths or critical dimensions of 0.18 xcexcm or less. The scaling rules that apply to these small devices call for very thin gate oxide layers, which have grown smaller with each generation of MOS integrated circuits. The thickness of gate oxides is made as small as possible, thereby increasing switching speed. Conventional gate oxide layers may be inadequate in several respects as dimensions are continuously scaled.
Extremely thin silicon dioxide gate dielectrics exhibit undesirable phenomena such as quantum-mechanical tunneling. In the classical sense, the oxide represents a relatively impenetrable barrier to injection of electrons into the conduction-band of the silicon if they possess kinetic energies smaller than 3.1 eV. However, the electron exhibits a finite probability of crossing the barrier even if the electron does not possess sufficient kinetic energy. This probability increases with larger gate electric fields and/or thinner gate oxides. For oxide thicknesses smaller than 3 nm the direct tunneling current becomes large enough that it removes carriers faster than they can be supplied by thermal generation. As a result, silicon dioxide gate dielectrics are likely to reach a lower scaling limit of about 1.5 nm to 2 nm.
Another problem with thin gate oxides is their susceptibility to dopant diffusion from the overlying gate electrode. A polysilicon gate electrode layer is typically doped with boron for its enhanced conductivity. As the gate oxide thickness is scaled down, boron can easily penetrate through the gate oxide, resulting in instabilities in device properties. Boron penetration into gate dielectrics has such undesirable consequences as positive shifts in threshold voltage, increases in sub-threshold swing, increases in charge trapping, decreases in low-field hole mobility, and degradation of current drive due to polysilicon depletion in p-MOSFETs.
Efforts to address deficiencies of silicon dioxide include nitrogen incorporation into the gate dielectric. Silicon nitride (Si3N4) has a higher dielectric constant than SiO2, theoretically enabling thinner equivalent oxide thickness for gate dielectrics that are not tunnel-limited, and furthermore serves as an effective barrier against impurity diffusion. However, the interfaces between silicon nitride films and the underlying semiconductor substrate are generally of poor quality, resulting in a high density of charge trapping sites and pinholes, and attendant current leakage. As a consequence, attempts have been made to create SiO2 and Si3N4 hybrids, such as silicon oxynitride films, for use as gate dielectrics. Conventional methods of incorporating nitrogen into silicon oxide gate dielectrics are difficult to control, however, particularly for ultra-thin gate dielectrics of future generation devices
Other solutions to scaling problems include the use of high permittivity materials (high K), such as tantalum pentoxide, strontium bismuth tantalate (SBT), barium strontium tantalate (BST), etc. While exhibiting greatly increased dielectric strength, these materials have been difficult to integrate with existing fabrication technology.
Another issue raised by the continual scaling of integrated circuit dimensions is the difficulty of producing adequately conductive metal lines for wiring the circuitry within integrated circuits. One manner of simplifying the process of metallization is by employing damascene techniques. Rather than depositing blanket metal layers and etching away excess metal to leave wiring patterns, damascene processing involves forming templates for wiring by way of trenches in an insulating layer. Metal overfills the trenches and a polishing step removes excess metal outside the trenches. Metal is thus left in a desired wiring pattern within the trenches. Where contact holes or vias extending from the floor of the trenches to lower conductive elements are simultaneously filled with metal, the method is known as dual damascene processing.
Unfortunately, scaling introduces difficulties with damascene processes, particularly when fast diffusing metals like copper are employed for the metal lines and contacts. In order to prevent peeling of metal lines from the surrounding insulation and to prevent diffusion spikes causing shorts across lines, one or more lining layers are formed within the trenches (and vias, in dual damascene processing) prior to metal fill. Typically, metal adhesion layers and metal nitride barrier layers are employed. A metal seed layer may also be needed if the trenches are to be filled by electroplating.
These lining layers occupy a considerable volume of the available trenches, reducing room available for the more highly conductive metal filler. Conductivity is thus reduced relative to the same trenches filled completely with metal. Moreover, employing metal nitride liners, though advantageously containing the metal filler and preventing short circuits, has been known to induce electromigration during circuit operation, leading to voids and further reduced conductivity along the metal lines.
Accordingly, a need exists for thin films that overcome problems associated with gate dielectrics constructed of traditional materials such as silicon nitride and silicon oxide. A need also exists for improved structures and methods for containing metal within damascene trenches without excessive losses in conductivity.
The aforementioned and other needs are satisfied by several aspects of the present invention.
In accordance with one aspect of the invention, a thin film is provided in an integrated circuit. The film has a small thickness, defined between an upper surface and a lower surface. A controlled, varying composition is provided through this small thickness. Exemplary thicknesses are preferably less than about 100 xc3x85, more preferably less than about 50 xc3x85 and can be on the order of 10 xc3x85.
In accordance with one embodiment, the film comprises a gate dielectric for an integrated thin film transistor. In one arrangement, a silicon oxide layer is provided with a graded concentration of nitrogen. Despite the thinness of the layer, such a gradient can be maintained. Advantageously, a relatively pure silicon dioxide can be provided at the lower level for a high quality channel interface, while a high nitrogen content at the upper surface aids in resisting boron diffusion from the polysilicon gate electrode. In another arrangement, other dielectric materials can be mixed in a graded fashion to obtain desirable interface properties from one material and desirable bulk properties from another material, without undesirable sharp interfaces within the gate dielectric. For example, Al2O3 has a high dielectric constant and desirable interface properties, while ZrO2 has yet a higher dielectric constant, which is desirable for the xe2x80x9cbulkxe2x80x9d of the gate dielectric.
In accordance with a second embodiment, the film comprises a transition layer between a barrier film and a more conductive wiring material. In the illustrated embodiment, a thin metal nitride layer is provided with a graded concentration of copper. The nitride layer can be made exceedingly thin, leaving more room for more conductive metal within a damascene trench, for example. Advantageously, an effective diffusion barrier with metal nitride can be provided at the lower surface, while a high copper content at the upper surface provides the conductivity needed for service as an electroplating seed layer. The gradual transition also reduces electromigration, as compared to structures having sharp barrier-metal interfaces.
In accordance with another aspect of the invention, a method is provided for forming a thin film in an integrated circuit, with varying composition through its thickness. The method includes alternatingly introducing at least a first species and a second species to a substrate in each of a plurality of deposition cycles while the substrate is supported within a reaction chamber. A third species is introduced to the substrate in a plurality of the deposition cycles. The amount of the third species can vary in the different cycles in which it is introduced. Alternatively, the third species is supplied in its own source gas pulse, which pulse is employed with increasing or decreasing frequency as the thin film deposition proceeds (e.g., none during a first stage, every fourth cycle during a second stage, every cycle during a third stage, etc.).
Advantageously, the amount of the impurity varies between zero during early deposition cycles and a maximum amount during late deposition cycles. In one example, a silicon source gas adsorbs upon the substrate in a first phase of each cycle, while an oxidant source gas in a second phase of the cycle forms silicon oxide. After a relatively pure silicon oxide covers the substrate surface, small amounts of a nitrogen source gas are introduced during the second phase. The amount of nitrogen source gas increases with each cycle thereafter. The amount of oxidant during the second phase can also decrease, such that a pure silicon nitride upper surface most preferably results, with graded nitrogen content between the upper and lower surfaces of the dielectric. Similarly, in a second example, tungsten, reducing and nitrogen sources provide metal nitride in first through third phases. A copper source and reducing agents in fourth and fifth phases provide copper. In successive cycles, the relative proportions of the first through third phases (producing no more than about one monolayer of WN) and the fourth through fifth phases (producing no more than about one monolayer of Cu) changed. The increases/reductions can be altered step-wise, e.g., every two cycles, every three cycles, every five cycles, etc.
According to another aspect of the invention, selectively introduced impurity phases or pulses can replace atoms of a previous phase in a thermodynamically favored substitution reaction. Grading can be accomplished by varying the frequency of the impurity phase through the atomic layer deposition process. Alternatively, the frequency of the impurity phase can be kept constant while the duration of the impurity phase is varied throughout the deposition process, or a combination of varying frequency and duration can be employed.
Due to the fine control provided by atomic layer deposition, this grading can be provided in very thin layers. Moreover, the low temperatures during the process enables maintenance of the desired impurity content profile.